Wirebonding in integrated circuit packages is one of the sources of intensive labor and of yield defects. Furthermore, conventional chip-on-board packages and overmolded pad array carriers (OMPAC) have a profile or thickness that could be reduced. The cost of manufacturing flip chip and chip-on-board packages could be reduced if fine pitched lines and spaces were not required on a printed circuit board. Both flip chip and chip-on-board packages require fine pitched printed circuit boards or substrates. Further expense is found in the requirement of gold plating for wirebonding on chip-on-board packages.
Flip-chip and chip-on-board packages also have mechanical and electrical disadvantages. For instance, with flip-chip packages there are tiny solder joints and heat dissipation problems. With chip-on-board packages and other packages requiring wirebonding, electrical characteristics may vary due to the flexibility of conductor widths and materials and the inconsistency of wire lengths. Finally, many packages require the extra step of passivating die pad surface. Therefore, a need exists for a smaller profiled IC package that does not require fine pitched printed circuit boards or gold plating for wirebonding. Furthermore, a need exists for an IC package that has excellent mechanical and electrical characteristics that does not require passivation for die pads and overcomes the problems described above.